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Altera_Forum
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14 years ago

System-console with FPGA Stratix IV GT 230

I use a system-console with FPGA Stratix IV GT 230. After a few minutes FPGA Stratix IV GT 230 loses configuration. I use the card HTG-S4GT-PCIE-230 HiTech Global. A similar configuration SOPC Builger systems on Stratix II GX 90 works flawlessly.

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  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I use a system-console with FPGA Stratix IV GT 230. After a few minutes FPGA Stratix IV GT 230 loses configuration. I use the card HTG-S4GT-PCIE-230 HiTech Global. A similar configuration SOPC Builger systems on Stratix II GX 90 works flawlessly.

    --- Quote End ---

    Its highly unlikely that the problem has anything to do with using system-console. Its more likely to be hardware related.

    1) Does your design use lots of power? If the hardware (FPGA die temperature) is getting too hot, then perhaps the HiTech design has a hardware monitor that is disabling the FPGA. If the power supplies have current sensors, then perhaps you are tripping them.

    2) Is the FPGA nCONFIG pin picking up noise? If this signal is asserted low, then the FPGA will clear its configuration.

    3) Is there a configuration controller on the board? Perhaps you are accidentally communicating with it, or requesting a reconfiguration? Are you using a top-level design where all pins used on the FPGA on the PCB are assigned, regardless of whether your design uses them or not? Are the unused pins driven to deasserted levels?

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    Thank you Dave! On the basis of board HTG-S4GT-PCIE -230 I developed a fairly complex project, which consists of a controller PCI Express 2.0 x8, MAC 10G, NiosII etc. All of this works stable. Then there is a need to observe some of the registers and memory locations and I decided to use the system-console. In the single appeals operations such as master _read _32/master _write _32 are working normally. The problem manifested itself when I wrote the script in tcl using after time proc _name. After a few minutes (from 1 to 10) FPGA configuration has to lose. I tried to make a very simple project and the problem persists. The board ieetsya configurator MAXII. It manages the configuration pins nconfig etc. I tried hard to connect the findings programming inactive levels - does not help problem repeat.

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Then there is a need to observe some of the registers and memory locations and I decided to use the system-console. In the single appeals operations such as master _read _32/master _write _32 are working normally. The problem manifested itself when I wrote the script in tcl using after time proc _name. After a few minutes (from 1 to 10) FPGA configuration has to lose. I tried to make a very simple project and the problem persists.

    --- Quote End ---

    System-console can also be used via TCP/IP and NIOS II. I would try that next. Perhaps the issue is related to the use of the JTAG interface.

    The Tcl 'after' statement should not cause any issues. That should just be delaying Tcl. However, system-console is not a real Tcl console, as fileevent does not work, info nameofexecutable does not work, Tk does not work, and a few other standard Tcl things I've tried.

    When system-console has an open connection over JTAG is polls the JTAG interface a lot. Perhaps by using an after statement in your Tcl, you are somehow stalling the internal system-console event loop, and that is the root cause of your issue.

    The other JTAG option you can try is the SLD Virtual JTAG component, and then access that from quartus_stp. That application only generates JTAG activity when you issue Tcl commands.

    Cheers,

    Dave