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RBash's avatar
RBash
Icon for Occasional Contributor rankOccasional Contributor
6 years ago
Solved

Synthesizing design for PAC with Arria 10 GX fails

I'm trying to synthesize a design for a PAC with Arria 10 GX, but get the following messages when the synthesis script finishes. Since the error message doesn't give any particular information, I don...
  • JohnT_Altera's avatar
    JohnT_Altera
    6 years ago

    Hi,

    Thanks for the report file. It looks like there is a conflict on the your Quartus design where the IP name use is the same.

    Below is the error message when Quartus Synthesis is performed. You will need to make some changes on your design so that it is not using the same file name.

    Error (19021): The same file name "mm_bridge_0" is used for different IP files. The same name cannot be used for more than one IP file.

JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Could you provide your system variable before you compile your design? I would like to make sure that the environment is correct.

RBash's avatar
RBash
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

The following is the output of printenv. I removed other environment variables that are not related to Intel FPGA, if you're looking for a specific variable please let me know.

QSYS_ROOTDIR=/winhomes/rb274/intelFPGA_pro/18.0/qsys/bin
INTELFPGAOCLSDKROOT=/opt/fpga/inteldevstack/intelFPGA_pro/hld
QUARTUS_HOME=/opt/fpga/inteldevstack/intelFPGA_pro/quartus
OPAE_PLATFORM_ROOT=/opt/fpga/inteldevstack/a10_gx_pac_ias_1_2_pv
FPGA_BBB_CCI_SRC=/winhomes/rb274/intel-fpga-bbb-master
AOCL_BOARD_PACKAGE_ROOT=/opt/fpga/inteldevstack/a10_gx_pac_ias_1_2_pv/opencl/opencl_bsp