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RBash's avatar
RBash
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Synthesizing design for PAC with Arria 10 GX fails

I'm trying to synthesize a design for a PAC with Arria 10 GX, but get the following messages when the synthesis script finishes. Since the error message doesn't give any particular information, I don...
  • JohnT_Altera's avatar
    JohnT_Altera
    5 years ago

    Hi,

    Thanks for the report file. It looks like there is a conflict on the your Quartus design where the IP name use is the same.

    Below is the error message when Quartus Synthesis is performed. You will need to make some changes on your design so that it is not using the same file name.

    Error (19021): The same file name "mm_bridge_0" is used for different IP files. The same name cannot be used for more than one IP file.

JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

From the error message, it failed to synthesis the partition. You might need to try out each to compile each of your partition or module.

RBash's avatar
RBash
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thank you for your response. The steps I take now are the following:

$ afu_synth_setup --source=rtl/filelist.txt build_fpga
$ cd build_fpga/
$ $OPAE_PLATFORM_ROOT/bin/run.sh

So what you suggest is I compile each of my .qsys files manually using Quartus instead? And then how do I combine them all to generate a programming bitstream? Can you please point me to a document on how to do that if there exists one?

Thanks.