synthesis - entity with multiple architectures

Hello there,

I have a little problem synthesizing a vhdl design

which has 2 architectures for the same entity (I use Quartus II 13.0.0).

I have 2 files for the 2 architectures of the entity, each file having the same entity declaration at the start of file.

With my modelsim simulation everything runs fine:

I have put a configuration to the top level

and with that I can select the architecture in use:

******************

File: SumAbsDifference_Arch00.vhd

...

ENTITY hk_SumAbsDifference is

PORT (

--control signals

clr_n : IN STD_LOGIC;

clk : IN STD_LOGIC;

...

);

ARCHITECTURE arch0 OF hk_SumAbsDifference IS

signal referenceDataArray : hk_TemplateArray;

BEGIN

...

END arch0;

******************

File: SumAbsDifference_Arch01.vhd

...

ENTITY hk_SumAbsDifference is

PORT (

--control signals

clr_n : IN STD_LOGIC;

clk : IN STD_LOGIC;

...

);

ARCHITECTURE arch1 OF hk_SumAbsDifference IS

signal referenceDataArray : hk_TemplateArray;

BEGIN

...

END arch1;

******************

toplevel.vhd

...

configuration cfg_TB1 of hk_SingleTemplateMatching is

for arch1

for SumAbsDifference_tb : hk_SumAbsDifference

use entity work.hk_SumAbsDifference(arch0);

-- use entity work.hk_SumAbsDifference(arch1);

end for;

end for;

end;

******************

However the QII synthesis produces a

Error (10430): VHDL Primary Unit Declaration error at SumAbsDifference_Arch01.vhd(30): primary unit "hk_SumAbsDifference" already exists in library "work"

which I think is due to the 2 identical entity declarations in the two files (however with different architecture name)

Well of course there are several ways to patch the problem

e.g. by using two different entity names

or by only selecting SumAbsDifference_Arch01.vhd in the project's file list.

But is there a clean (best practice) way for doing this by configuration ?

Thanks and kind regards !