synthesis - entity with multiple architectures

I solved the problem.

I put the entity to an extra file:

******************

File: SumAbsDifference_Entity.vhd

ENTITY hk_SumAbsDifference is

PORT (

clr_n : IN STD_LOGIC;

clk : IN STD_LOGIC;

...

);

END hk_SumAbsDifference;

******************

and the two architectures (without entity ) in the two files

******************

File: SumAbsDifference_Arch00.vhd

ARCHITECTURE arch0 OF hk_SumAbsDifference IS

signal referenceDataArray : hk_TemplateArray;

BEGIN

...

END arch0;

******************

File: SumAbsDifference_Arch01.vhd

ARCHITECTURE arch1 OF hk_SumAbsDifference IS

signal referenceDataArray : hk_TemplateArray;

BEGIN

...

END arch1;

******************

The configuration I had to put into the .vhd where the component is instantiated.

******************

File: SingleTemplateMatching.vhd

configuration cfg_TB1 of hk_SingleTemplateMatching is

for ar1

for SumAbsDifference_tb : hk_SumAbsDifference

-- use entity work.hk_SumAbsDifference(arch0); -- general n-Bit version NOT optimized

use entity work.hk_SumAbsDifference(arch1); -- non lossy version 15 bit

end for;

end for;

end;

******************

otherwise I would have to stepwise go through all the submodules (TL->Nios->DMAComponent->HWTop->...) and create configurations

which one calls the other

(like in: http://www.altera.com/support/kdb/solutions/rd07032012_70.html )

Thanks for your quick responses (the basic idea was, that a second entity definition is forbidden even if it is identical to the first).

Kind regards