You mean error file? I suppose modelsim creates this.
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "12/17/2013 11:18:31"
// Verilog Self-Checking Test Bench (with test vectors) for design : freq_dev
//
// Simulation tool : 3rd Party
//
`timescale 1 ps/ 1 ps
module freq_dev_vlg_sample_tst(
input,
sampler_tx
);
input input;
output sampler_tx;
reg sample;
time current_time;
always @(input)
begin
if ($realtime > 0)
begin
if ($realtime == 0 || $realtime != current_time)
begin
if (sample === 1'bx)
sample = 0;
else
sample = ~sample;
end
current_time = $realtime;
end
end
assign sampler_tx = sample;
endmodule
module freq_dev_vlg_check_tst (
output,
sampler_rx
);
input output;
input sampler_rx;
reg output_expected;
reg output_prev;
reg output_expected_prev;
reg last_output_exp;
reg trigger;
integer i;
integer nummismatches;
reg on_first_change ;
initial
begin
trigger = 0;
i = 0;
nummismatches = 0;
on_first_change = 1'b1;
end
// update real /o prevs
always @(trigger)
begin
output_prev = output;
end
// update expected /o prevs
always @(trigger)
begin
output_expected_prev = output_expected;
end
// expected output
initial
begin
output_expected = 1'bX;
end
// generate trigger
always @(output_expected or output)
begin
trigger <= ~trigger;
end
always @(posedge sampler_rx or negedge sampler_rx)
begin
`ifdef debug_tbench
$display("Scanning pattern %d @time = %t",i,$realtime );
i = i + 1;
$display("| expected output = %b | ",output_expected_prev);
$display("| real output = %b | ",output_prev);
`endif
if (
( output_expected_prev !== 1'bx ) && ( output_prev !== output_expected_prev )
&& ((output_expected_prev !== last_output_exp) ||
on_first_change)
)
begin
$display ("ERROR! Vector Mismatch for output port output :: @time = %t", $realtime);
$display (" Expected value = %b", output_expected_prev);
$display (" Real value = %b", output_prev);
nummismatches = nummismatches + 1;
on_first_change = 1'b0;
last_output_exp = output_expected_prev;
end
trigger <= ~trigger;
end
initial
begin
$timeformat(-12,3," ps",6);
# 1000000;
if (nummismatches > 0)
$display ("%d mismatched vectors : Simulation failed !",nummismatches);
else
$display ("Simulation passed !");
$finish;
end
endmodule
module freq_dev_vlg_vec_tst();
// constants
// general purpose registers
reg input;
// wires
wire output;
wire sampler;
// assign statements (if any)
freq_dev i1 (
// port map - connection between master ports and signals/registers
.\input (input),
.\output (output)
);
// input
always
begin
input = 1'b0;
input =# 25000 1'b1;
# 25000;
end
freq_dev_vlg_sample_tst tb_sample (
.input(input),
.sampler_tx(sampler)
);
freq_dev_vlg_check_tst tb_out(
.output(output),
.sampler_rx(sampler)
);
endmodule
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