Altera_ForumHonored Contributor12 years agoSyntax error, unexpected integer number, expecting identifier Hello there. I am starter at FPGA. I've advanced digital design course at my M.Sc class. Lecturer give us a homework about on Quartus 2,creating schematic designs, graphical test vector and simulate...Show Moremultiple-attachments.zip400 KB
Altera_ForumHonored Contributor12 years agoYou cannot have an input called input - it is a reserved word in verilog.
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