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Altera_Forum
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12 years ago

Syntax error, unexpected integer number, expecting identifier

Hello there. I am starter at FPGA. I've advanced digital design course at my M.Sc class. Lecturer give us a homework about on Quartus 2,creating schematic designs, graphical test vector and simulate...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

the problem is that you named the project 21mux. To work in modelsim it has to convert the schematic to an HDL (VHDL or verilog), which appears to be verilog in your case. Neither HDL allow names to start with numbers.