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jjxichn's avatar
jjxichn
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1 year ago
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subtractor in quartus

Hello All, I am new to Altera and I am using Agilex to do some interesting stuff. Does any one know whether Quartus Prime 20.4 have ip core to do subtraction with embedded pipelines? I only see Multiply Adder Intel FPGA IP core inside it. What is the best way to do subtraction? Shall I write it in verilog explictly?

Hdl
  • FvM's avatar
    FvM
    1 year ago

    Hi,

    you can use Fixed Point Functions IP, Parrallel Add. Substraction is generated by giving a minus sign to one input parameter.

    It has all options to set different pipeline levels and estimates speed.

4 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago
    Hi,
    did you notice the "+/-" symbol in DSP block schematic? Fixed and float IP perform both add and substract.
    • jjxichn's avatar
      jjxichn
      Icon for New Contributor rankNew Contributor
      1 year ago

      That +/- is only for DSP. But I prefer to use ALMs. So I am curious if we can use any IPs to do substraction using ALMs as a pipelined fashion?

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,

    you can use Fixed Point Functions IP, Parrallel Add. Substraction is generated by giving a minus sign to one input parameter.

    It has all options to set different pipeline levels and estimates speed.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    Do you have any further update or concern?


    Thanks,

    Regards,

    Sheng