Subtetly : Modelsim misses signal events (VHDL)

Question

Hi, I have encoutered a strange behaviour in modelsim : few signals are not properly read in VHDL process.

I feel that this behaviour only occures when you create stimuli by macro.

I reproduce by

force -freeze sim:/my_entity/my_signal 1 0

I can't reproduce by

force -freeze sim:/my_entity/my_signal 1 20 ns

Very hard to discover when you first trust the simulator.

altera_forum · Answer

I suggest bringing up the problem with mentor.

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