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Altera_Forum's avatar
Altera_Forum
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10 years ago

Subprograms for bus functional model

Hi,

I have a problem that is driving me crazy! I hope someone can help me.

I am trying to make a bus functional model for simulation and using VHDL 2008 is fine.

The subprogram interface should look something like:

bfm_read(address,read_data) or read_data=bfm_read(address)

bfm_write(address,write_data)

These subprograms will be used in a testbench so somehow these subprograms must manipulate the bus signals for the entities instantiated in the testbench.

I should add I have done it by making an entity bfm and defining a procedure in the stimulus process in the testbench. But I would like to somehow move the subprograms to the bfm to make the it more modular.

I have looked into protected classes but I can't see how to connect the bfm bus signals using that approach.

Thanks!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You can create VHDL BFMs using two main techniques;

    1. An array of global signals, eg., see the Altera Avalon-MM BFM source code and tutorial I wrote (link to PDF and source on this page)

    https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

    2. Use a resolved signal and pass that as an extra argument

    Download

    https://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104code_hawkins_2015.zip

    and look at the Avalon-MM BFM code I wrote in

    ESC-104Code_Hawkins_2015.zip\dsp_tutorial\vhdl\lib\packages\test

    ESC-104Code_Hawkins_2015.zip\dsp_tutorial\vhdl\lib\altera_avalon\test

    If you've ever written "object-oriented C code" you'll appreciate that the resolved signal is acting like a reference to the BFM.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    you can manipulate signals in a procedure. E.g. 

    PROCEDURE ChangeOutputAfterClock(
  SIGNAL iSysClk               : IN  STD_LOGIC;
  SIGNAL oSource_Data          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
) IS
BEGIN
  -- initialize all output values
  oSource_Data          <= (OTHERS => '0');
  -- wait for one clock cycle to process
  WAIT UNTIL RISING_EDGE(iSysClk);
  -- change output value
  oSource_Data          <= (OTHERS => '1');
END PROCEDURE;