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Altera_Forum's avatar
Altera_Forum
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11 years ago

Subprograms for bus functional model

Hi, I have a problem that is driving me crazy! I hope someone can help me. I am trying to make a bus functional model for simulation and using VHDL 2008 is fine. The subprogram inte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

you can manipulate signals in a procedure. E.g. 

PROCEDURE ChangeOutputAfterClock(
  SIGNAL iSysClk               : IN  STD_LOGIC;
  SIGNAL oSource_Data          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
) IS
BEGIN
  -- initialize all output values
  oSource_Data          <= (OTHERS => '0');
  -- wait for one clock cycle to process
  WAIT UNTIL RISING_EDGE(iSysClk);
  -- change output value
  oSource_Data          <= (OTHERS => '1');
END PROCEDURE;