Struggling with Quartus II

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Hi All,

I am a new user to Altera's Quartus II and to FPGA's in general.

I have posted already on a similar matter, but had no replies so thought I'd try again.

I am using the FTDI Morph-IC-II board, and am struggling to get the communications between the Altera Cyclone-II FPGA and the FTDI FT2232 chip to work properly.

I configured the FTDI chip for communication using the synchronous 245 FIFO mode to interface with the FPGA.

I also have made a simple quartus II design which only has one Warning and as that is "warning: feature logiclock is only available with a valid subscription license. you can purchase a software subscription to gain full access to this feature." I should be fine to ignore it.

The thing that is confusing me most, is that when I do not have anything on the FPGA, the RXF# and TXE# signals which go between the FTDI chip and the FPGA work correctly. However when I try to impliment my design onto the FPGA these signals are held high.

I think I must have a problem with how I have set up the pins in my quartus II design, but I have been through many of the tutorials and web/e seminars and feel I am doing as I have been shown in the examples. However I am thoroughly stuck and slowly getting annoyed at the Altera software, as no matter what I do, even with no errors, nothing seems to be workin.

Any help, advice or guidance is very welcome and extremely appreciated!

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Hi,

yes, your are right you can ignore the mentioned Warning. It is a feature for grouping parts of your design together.

What do you mean with " I do not have anything on the FPGA", FPGA not programmed ?

Did you run a simulation of your design ? Can you be sure it is functional ?

BTW: Have a look to your Quartus default setting of un-used pins.

Assignments -> Settings -> Device -> Device & Pin options -> unused pins

Should be set to "Tri-stated input with weak-pull up"

Kind regards

GPK

--- Quote Start ---

Hi,

yes, your are right you can ignore the mentioned Warning. It is a feature for grouping parts of your design together.

What do you mean with " I do not have anything on the FPGA", FPGA not programmed ?

Did you run a simulation of your design ? Can you be sure it is functional ?

BTW: Have a look to your Quartus default setting of un-used pins.

Assignments -> Settings -> Device -> Device & Pin options -> unused pins

Should be set to "Tri-stated input with weak-pull up"

Kind regards

GPK

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Yes sorry I did mean that with my FPGA not programmed, when I probe the RXF and TXE lines they behave as normal, but when my FPGA is programmed they are held high.

Yes I had already changed my unassigned pins to "Tri-stated input with weak-pull up"

I have been struggling with the simulation stuff as I just got errors saying "Check the NativeLink log file <my filepath> _nativelink_simulation.rpt

for detailed error messages" whenTools>Run EDA Simulation tool>EDA RTL Simulation

When opening the _nativelink_simulation.rpt file it gives the messages:

info: start nativelink simulation process

error: nativelink did not detect any hdl files in the project

error: nativelink simulation flow was not successful

================the following additional information is provided to help identify the cause of error while running nativelink scripts=================

nativelink tcl script failed with errorcode: none

nativelink tcl script failed with errorinfo: nativelink did not detect any hdl files in the project

invoked from within

"if ![qmap_successfully_completed] {

nl_postmsg error "error: run analysis and elaboration successfully before starting rtl nativelink simulation"..."

(procedure "run_eda_simulation_tool" line 170)

invoked from within

"run_eda_simulation_tool eda_opts_hash"

As I am not very familiar with VHDL, I had created my design using the schematic view. Due to this I have only a .bdf and a .sdc file on my files tab and have no HDL files as I am only using primitives such as input, output and bidir pins. some alt_iobuf buffers, some DFFs and some basic logic NOT and OR2 gates.

All my pins are assigned, timequest is happy with my timing, but I can't seem to get any simulation to work, so I had tried to see whether I could program the FPGA and use a 4 channel scope to check that the logic was working. But all the pins shown on the scope appear high when the FPGA has been programmed. Including ones that are connected to the FT2232 chip. I have assigned the signals to the corresponding pin numbers given in the MORPH-IC-II data sheet.

I am using an EP2C5F256C8N cyclone II.

I am unsure what to do at the moment... so if anyone knows how I can get any simulations working, just so that I can kind of see whats going on it would be much appreciated!!

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Yes sorry I did mean that with my FPGA not programmed, when I probe the RXF and TXE lines they behave as normal, but when my FPGA is programmed they are held high.

Yes I had already changed my unassigned pins to "Tri-stated input with weak-pull up"

I have been struggling with the simulation stuff as I just got errors saying "Check the NativeLink log file <my filepath> _nativelink_simulation.rpt

for detailed error messages" whenTools>Run EDA Simulation tool>EDA RTL Simulation

When opening the _nativelink_simulation.rpt file it gives the messages:

info: start nativelink simulation process

error: nativelink did not detect any hdl files in the project

error: nativelink simulation flow was not successful

================the following additional information is provided to help identify the cause of error while running nativelink scripts=================

nativelink tcl script failed with errorcode: none

nativelink tcl script failed with errorinfo: nativelink did not detect any hdl files in the project

invoked from within

"if ![qmap_successfully_completed] {

nl_postmsg error "error: run analysis and elaboration successfully before starting rtl nativelink simulation"..."

(procedure "run_eda_simulation_tool" line 170)

invoked from within

"run_eda_simulation_tool eda_opts_hash"

As I am not very familiar with VHDL, I had created my design using the schematic view. Due to this I have only a .bdf and a .sdc file on my files tab and have no HDL files as I am only using primitives such as input, output and bidir pins. some alt_iobuf buffers, some DFFs and some basic logic NOT and OR2 gates.

All my pins are assigned, timequest is happy with my timing, but I can't seem to get any simulation to work, so I had tried to see whether I could program the FPGA and use a 4 channel scope to check that the logic was working. But all the pins shown on the scope appear high when the FPGA has been programmed. Including ones that are connected to the FT2232 chip. I have assigned the signals to the corresponding pin numbers given in the MORPH-IC-II data sheet.

I am using an EP2C5F256C8N cyclone II.

I am unsure what to do at the moment... so if anyone knows how I can get any simulations working, just so that I can kind of see whats going on it would be much appreciated!!

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Hi,

unfortunately I'm not an expert for the native link flow and conversion of bdf's to Vhdl.

If you don't use Quartus 10.0 and the design needs not to complex input pattern you can

give the simple Quartus build-in simulator a try. In normal I would not recommand the use, because it is not supported in the future and has limitations. But may you can see

what is going wrong.

Kind regards

GPK

I'll give it a go.

Cheers for your help :)