Struggling with Quartus II

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Yes sorry I did mean that with my FPGA not programmed, when I probe the RXF and TXE lines they behave as normal, but when my FPGA is programmed they are held high.

Yes I had already changed my unassigned pins to "Tri-stated input with weak-pull up"

I have been struggling with the simulation stuff as I just got errors saying "Check the NativeLink log file <my filepath> _nativelink_simulation.rpt

for detailed error messages" whenTools>Run EDA Simulation tool>EDA RTL Simulation

When opening the _nativelink_simulation.rpt file it gives the messages:

info: start nativelink simulation process

error: nativelink did not detect any hdl files in the project

error: nativelink simulation flow was not successful

================the following additional information is provided to help identify the cause of error while running nativelink scripts=================

nativelink tcl script failed with errorcode: none

nativelink tcl script failed with errorinfo: nativelink did not detect any hdl files in the project

invoked from within

"if ![qmap_successfully_completed] {

nl_postmsg error "error: run analysis and elaboration successfully before starting rtl nativelink simulation"..."

(procedure "run_eda_simulation_tool" line 170)

invoked from within

"run_eda_simulation_tool eda_opts_hash"

As I am not very familiar with VHDL, I had created my design using the schematic view. Due to this I have only a .bdf and a .sdc file on my files tab and have no HDL files as I am only using primitives such as input, output and bidir pins. some alt_iobuf buffers, some DFFs and some basic logic NOT and OR2 gates.

All my pins are assigned, timequest is happy with my timing, but I can't seem to get any simulation to work, so I had tried to see whether I could program the FPGA and use a 4 channel scope to check that the logic was working. But all the pins shown on the scope appear high when the FPGA has been programmed. Including ones that are connected to the FT2232 chip. I have assigned the signals to the corresponding pin numbers given in the MORPH-IC-II data sheet.

I am using an EP2C5F256C8N cyclone II.

I am unsure what to do at the moment... so if anyone knows how I can get any simulations working, just so that I can kind of see whats going on it would be much appreciated!!

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Hi,

unfortunately I'm not an expert for the native link flow and conversion of bdf's to Vhdl.

If you don't use Quartus 10.0 and the design needs not to complex input pattern you can

give the simple Quartus build-in simulator a try. In normal I would not recommand the use, because it is not supported in the future and has limitations. But may you can see

what is going wrong.

Kind regards

GPK