Stratix V, DDR3L SDRAM: Error (169026): Pin oct_rzqin is incompatible with I/O bank

Hi,

I'm trying to synthesize a design for Stratix V (5SGXEA7f40) with Quartus V12. I've lots of components in the design, like transceivers and LVDS ports and there are also two DDR3L SDRAM interfaces.

I've generated the Controller with Megawizard and connected the RZQ ports of both controllers. One to RZQ_1 in the Bank 4A, the other to RZQ_4 in the Bank 7A. The IO standard for all banks, used for DDR3L is assigned to SSTL-135.

I can synthesize the design, but the Quartus V12 instantiates an additional pin named termination_block0~_rzq_pin and uses one of the remaining RZQ pins as the OCT termination input pin with the IO standard SSTL-135!! Which means I've to use all other pins in this bank with the same IO standard.

I thought the termination controller used for the SDRAM controller is connected to rzq pin of the controller.

Or do I actually need an additional one? Is the generated OCT block needed for other interfaces?

Does anybody know if it is possible and how to assign another IO Standard to the pin of the generated termination control block than SSTL-135, if I use DDR3L SDRAM in my design?

Thank you,