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Altera_Forum
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13 years ago

Stratix V, DDR3L SDRAM: Error (169026): Pin oct_rzqin is incompatible with I/O bank

Hi, I'm trying to synthesize a design for Stratix V (5SGXEA7f40) with Quartus V12. I've lots of components in the design, like transceivers and LVDS ports and there are also two DDR3L SDRAM int...
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Altera_Forum
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13 years ago

I had other IOs with the IO-Standard SSTL-135. In default setting, this IO standard termination will generated with calibration and therefore another termination block.

Adding the "without termination" assignment for those pins solved the problem.

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set_instance_assignment -name OUTPUT_TERMINATION "SERIES 34 OHM WITHOUT CALIBRATION" -to I2C_SDA

...

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