Forum Discussion
Stratix 10 Transceiver toolkit
- 2 years ago
Hi,
I have a look into your IP design. I found that your IP design not meet below requirement. In the user guide, it has mentioned about that to enable Intel® Stratix® 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:
- Enable dynamic reconfiguration
- Enable Native PHY Debug Master Endpoint
- Enable capability registers
- Enable control and status registers
- Enable PRBS (Pseudo Random Binary Sequence) soft accumulators
For further information, you may refer to link below, Section 2.3.10, https://www.intel.com/content/www/us/en/docs/programmable/683621/current/dynamic-reconfiguration-parameters.html
Please do try enable the above options and compile the design again. Please do try run the system console again to see the error still exist anot.
Best regards,
zying
Hi,
I found that your design compilation was fail. Please make sure your design was compiled successfully, then can proceed to the programmer and system console.
Best regards,
zying
- SDe_J2 years ago
Occasional Contributor
Ah, my mistake. Attached to this message is a new qar archive that I confirmed works.
The transceiver IPs are instantiated in "interlaken_MGT.vhd".
The top level entity is in "4.._fpga_target_hw_devkit_s10_devkit_top_ent.vhd", but the architecture is in a separate file: "interlaken_MGT_arch.vhd"
Thank you again for helping me!
- SDe_J2 years ago
Occasional Contributor
Hello Zying,
Have you had a chance to look at this design?