Stratix 10 Transceiver toolkit

Hi,

I have a look into your IP design. I found that your IP design not meet below requirement. In the user guide, it has mentioned about that to enable Intel® Stratix® 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:

• Enable dynamic reconfiguration
• Enable Native PHY Debug Master Endpoint
• Enable capability registers
• Enable control and status registers
• Enable PRBS (Pseudo Random Binary Sequence) soft accumulators

For further information, you may refer to link below, Section 2.3.10, https://www.intel.com/content/www/us/en/docs/programmable/683621/current/dynamic-reconfiguration-parameters.html

Please do try enable the above options and compile the design again. Please do try run the system console again to see the error still exist anot.

Best regards,

zying