Stratix 10 HPS DDR4 EMIF placement error

Hi ,

Sorry for the delay in getting back, was scrutinizing the pins with the team and doing testing on the Quartus fitter

To resolve the fitter error on the IO lane and tile, you will need to remove the pin assignment CLK_50_B2L in pin planner and let the fitter reassign it automatically (alternatively edit the qsf file, and remove the constraint "set_location_assignment PIN_BA27 -to CLK_50_B2F"

This is some others restrictions that was put in place in the requirements on banks 2M, 2L, 2N (other than the ones mentioned in the KDB )

On quartus 19.4 , probably I will check it later , as the KDB mention 19.1 and below, but i suspect additional requirements been put in place as well.

Thanks

Regards

Kian