Stratix 10 GX EMIF IP corrupting Host Boot code

Hi Adzim,

Following are the EMIF Interface Configuration steps that we followed.

1. Instantiate “External Memory Interfaces Intel Stratix 10 FPGA IP” from “Memory Interfaces and Controllers” library of IP Catalog
2. Applied “Stratix 10 GX H-Tile FPGA Development kit with DDR4 HiLo” Preset as shown in Snapshot “preset_cfg_changes_1.png”
3. Exported pll_ref_clk with name ddr_ref_clk
4. Specified connection from “rxm_bar0” of PCIe EP instance to “ctrl_amm_0” of “emif_s10_0” instance. And Tool identified two Errors
1. Error: gyann_fpga.emif_s10_0.ctrl_amm_0: Data width must be of power of two and between 8 and 4096
5. To overcome the Error, we switched to Controller Tab and set “Enable Error detection and Correction Logic with ECC” in “Configuration, status and Error handling” sub tab.
1. This setting changed the Avalon amm Data width from 576 to 512
6. Data corruption Warning
1. Warning: gyann_fpga.pcie_s10_hip_avmm_bridge_0.rxm_bar0/emif_s10_0.ctrl_amm_0: emif_s10_0.ctrl_amm_0 does not have byteenables. Writes from narrow master pcie_s10_hip_avmm_bridge_0.rxm_bar0 may result in data corruption
7. To overcome the Warning, we switched to “Memory” Tab, to reset “Write DBI” and set “Data mask” in “Topology” sub tab
1. Setting Data mask along with “Write DBI” threw Errors

No timing violations are seen in the Build reports.

We have not tested the EMIF IP standalone, We are working to try that after your suggestion.

We have captured videos of Successful reboot and failed reboot scenarios. During the failure, The Host just Shuts down and does not Power up at all.

I will share the videos if required over email.

Regards

Siva Kona