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aesq
New Contributor
New ContributorStratix 10 Dual port ram with byte enable
Hello, It is known that the Stratix 10 does not support true dual port ram with byte enable. But would it be possible to have a dual port ram with 2 different clocks, where one port uses the byte ...
aesqNew Contributor
New ContributorWhat I do is that I provide a dual port RAM RTL code to Synplify and the generated verilog netlist is used by Quartus.
Synplify says that dual port ram is not supported in Stratix 10, which is the case.
Same RTL code also fails when synthesized in Quartus.
Do you have any other RTL code proposal that Could be used and Working for Synplify and Quartus?
I cannot copy my code or attach it, it is blocked by the company...
