Strange State Machine Compilation - Compiler Bug?

Hello Axel,

I can contribute another interesting observation regrading your code example. In the detail below, you see that the if trafficlight_ena = '1' then condition is always true cause it is evaluated after the preceeding if trafficlight_ena = '0' then.

if trafficLight_ena = '0' then
	reset_timer_var := '1';
	state <= init;
else
	case state is
	when init =>
		output <= "00";
		if trafficLight_ena = '1' then -- always true, but...
			reset_timer_var := '1';
			state <= red;
		end if;

Whatever the compiler may synthezise from the redundant IF statement, it produces a third netlist variant if you omit it and a possible else state <= init statement. Try yourself. Furthermore, the coding differences from additional else in green and red state are vanishing. Somewhat surprizing.

I stumbled on the "dead code", when I tryed to understand, if the different netlists would cause identical behaviour.

Regards,

Frank