Strange state machine behavior

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You should look at the signal "state". It does not have an initial value.

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Yes it does. All types default to the left most value when uninitialised - which in this case is "idle"

I found the problem - its to do with the simmantics of the VHDL language.

Because you have set the clock and nsimb to rise and fall in unison (rather than have nsimb change with respect to the clock), the code actually sees nsimb as '1' when you see a rising edge on the wave window. If you look at the state signal, you will see it is changing at the same time as nsimb goes goes from 0=>1.

The best way to fix this will be to do one of the following:

1. Have nsimb and in_c change on the falling edge of the clock

1. Write a testbench in VHDL and have nsimb react to the clock, rather than directly stimulate it and dont use the force command.

So your code is working fine, your testing is not.

Secondly, I found a bug in your code. Because wrt_counter is an integer 32 downto 0 and addr is only 15 downto 0, your simulation fails when you try to write 16+ to the address.

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Yes it does. All types default to the left most value when uninitialised - which in this case is "idle"

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You are right for simulation, but I don't think this is guaranteed in all environments when you synthesize. I don't think the code is acceptable for an ASIC project.