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Altera_Forum
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15 years ago

Strange state machine behavior

When I'm trying to synthesize and simulate a block described in BINR2time.vhd, it looks like its state is late by one nsimb strobe or something like that. I want state state machine to switch into 'a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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You should look at the signal "state". It does not have an initial value.

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Yes it does. All types default to the left most value when uninitialised - which in this case is "idle"