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Altera_Forum's avatar
Altera_Forum
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10 years ago

Strange bus failure

I am using Quartus 2 schematic entry for my project. I have designed an RS232 uart and baud rate generator. On the board, there is a 4 digit LED display.

At the top level, if I connect the output bus of the RS232 receiver directly to the display circuitry bus, then it outputs the correct Hex value of every RS232 character it receives and does so reliably.

Also at the top level, if I connect a constant value bus to the input of the RS232 sender circuit, and a 1 Hz square wave as a trigger, it also correctly sends the constant every second to the computer.

However, when I remove the constant and connect the output of the receiver to both the display and the sender, suddenly, the circuit forgets how to work properly. Instead, the LED display displays erroneous values and the echoed characters are not correct.

I have tried triggering the sender with the 1Hz clock and also the RX_READY pulse from the receiver - neither work. The output bus from the receiver remains constant until a new character is received, so there are no timing issues with that.

I have also tried naming and un-naming the bus - no luck.

Could fan out be an issue here? Is there such a thing with FPGAs?

Could a schematic at a lower level with a bus with the same name cause a conflict with the current level?

There are no I/O ports in use except for the RxD and TxD plus the LED ports and the system clock. So the bus in question is completely internal.

Its compiling fine.

Anybody seen this before?

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  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I drew up a 16 input 2-1 multiplexor to replace the HDL mux and there was no difference. I did look at the netlist schematic viewer, but I am not familiar with that tool. Looks interesting though.

    Can you give me an example of what you mean by clock enables compared to logic clocks? Are you saying that I should change the prescalers to use synchronous dividers instead of asynchronous ones?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Sorry its HDL, but a clock enable would look something like this: 

    
signal clk_en : std_logic := '0';
process(clk)
begin
  if rising_edge(clk) then
    clk_en <= not clk_en;
    if clk_en = '1' then
      --stuff here happens at half of the clock speed of clk
    end if;
  end if;
end process;
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I redrew the clock circuit and several subdividers. I have attached one here. The old main clock was made from ripple counters and the new one is all synchronous. Even the carries are synchronous. I used the XOR method for most of them which results in a slower MAX_CLK, but it shouldn't be an issue here. The sum of products method of construction is faster, but not needed here.

    Each clock subdivider has a clock ENAble and a Terminal Count output. The TC output is high whenever this and all prior clock circuits are at terminal count. The ENA input is fed from the TC output of the previous divider. All clocks are synchronous.

    I am more familiar with verilog HDL.

    I think the synchronous dividers are what you were talking about. Please look at the attached schematic and let me know. For what its worth, it runs on the board.

    EDIT: The forum shrunk it, but you should still be able to see what's going on.

    EDIT2: The design failed when I changed to the HDL 74163 again.