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Honored Contributor
Honored ContributorStrange bus failure
I am using Quartus 2 schematic entry for my project. I have designed an RS232 uart and baud rate generator. On the board, there is a 4 digit LED display. At the top level, if I connect the...
Altera_ForumHonored Contributor
Honored ContributorI drew up a 16 input 2-1 multiplexor to replace the HDL mux and there was no difference. I did look at the netlist schematic viewer, but I am not familiar with that tool. Looks interesting though.
Can you give me an example of what you mean by clock enables compared to logic clocks? Are you saying that I should change the prescalers to use synchronous dividers instead of asynchronous ones?
