Strange bus failure

I redrew the clock circuit and several subdividers. I have attached one here. The old main clock was made from ripple counters and the new one is all synchronous. Even the carries are synchronous. I used the XOR method for most of them which results in a slower MAX_CLK, but it shouldn't be an issue here. The sum of products method of construction is faster, but not needed here.

Each clock subdivider has a clock ENAble and a Terminal Count output. The TC output is high whenever this and all prior clock circuits are at terminal count. The ENA input is fed from the TC output of the previous divider. All clocks are synchronous.

I am more familiar with verilog HDL.

I think the synchronous dividers are what you were talking about. Please look at the attached schematic and let me know. For what its worth, it runs on the board.

EDIT: The forum shrunk it, but you should still be able to see what's going on.

EDIT2: The design failed when I changed to the HDL 74163 again.