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Altera_Forum's avatar
Altera_Forum
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11 years ago

Strange bus failure

I am using Quartus 2 schematic entry for my project. I have designed an RS232 uart and baud rate generator. On the board, there is a 4 digit LED display. At the top level, if I connect the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Sorry its HDL, but a clock enable would look something like this: 


signal clk_en : std_logic := '0';
process(clk)
begin
  if rising_edge(clk) then
    clk_en <= not clk_en;
    if clk_en = '1' then
      --stuff here happens at half of the clock speed of clk
    end if;
  end if;
end process;