Forum Discussion
changdou013
New Contributor
New ContributorStitching user logic to M-series NoC
I am trying to stitch user logic to the M-series NoC example design[DDR]. Platform Designer validates the design and the design passes analysis and elaboration stage however fails in synthesis stage ...
sstrell
Super Contributor
Super ContributorCan you provide the full error message? Did validation pass in the NoC Assignment Editor? What do your assignments in the NoC Assignment Editor look like?
