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Altera_Forum's avatar
Altera_Forum
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16 years ago

sth about PLL dedicated routing resource

Hi, i met with a problem when using the altera PLL to generate a clock. Quartus II posted a warning message as below:

Warning: PLL "PLL_36M:uPLL_36M|altpll:altpll_component|altpll_5hv1:auto_generated|pll1" output port clk[1] feeds output pin MCLK_PLL_OUT~output via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance.

It seems that the PLL generated clock did not drive registers via the global dedicated routing resources, so there are hold violations in the clock path. But I don't know how to specify the dedicated routing resources.

PS: the device is Cyclone III.

Please help!

Thank you very much! :)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The warning refers to bringing the clock signal to an external pin. It has no relation to the internal registers.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    The warning refers to bringing the clock signal to an external pin. It has no relation to the internal registers.

    --- Quote End ---

    Hi, vjAlter, thank you for reply.

    You are absolutely right. The PLL generated clock directly drives an output pin, but I just don't understand, why it should drive an output pin via the dedicated routing resource? And as far as I know, the software globally recognize the PLL generated clock as global clock, so it should use the global routing resource, right? But how did the warning come? Does it have anything to do with the output pin assignment? How can I correct it? (I tried to put the output pin to the dedicated clock pin of the device, but they are all input pins.)

    Please show me a way and I'll appreciate it, thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    You are absolutely right. The PLL generated clock directly drives an output pin, but I just don't understand, why it should drive an output pin via the dedicated routing resource?

    --- Quote End ---

    The warning explains the reason. If you use non-dedicated PLL outputs, then jitter performance might suffer a bit.

    --- Quote Start ---

    And as far as I know, the software globally recognize the PLL generated clock as global clock, so it should use the global routing resource, right?

    --- Quote End ---

    Once again, global clock is an internal routing issue, it has no relation to the PLL dedicated external output.

    --- Quote Start ---

    Does it have anything to do with the output pin assignment? How can I correct it?

    --- Quote End ---

    Yes, of course it is the output pin assignment. No big deal if you can't change it. Most people ignore that warning.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Yes, of course it is the output pin assignment. No big deal if you can't change it. Most people ignore that warning.

    --- Quote End ---

    Hi, vjAlter, Thank you for your detailed explanation, I have found the solution just now.

    I turned to the pin document of the device and I found that there are PLL dedicated output pins!!

    If I change the pin assignment of the pin, the warning will disappear and what's more, I will get better output clock! :)

    Thank you so much!

    And here is another discussion on this topic and they solved it perfectly, hope it will be a good reference to you too. :)

    http://www.alteraforum.com/forum/showthread.php?t=5014 (http://www.alteraforum.com/forum/showthread.php?t=5014)