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Altera_Forum
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15 years ago

sth about PLL dedicated routing resource

Hi, i met with a problem when using the altera PLL to generate a clock. Quartus II posted a warning message as below: Warning: PLL "PLL_36M:uPLL_36M|altpll:altpll_component|altpll_5hv1:auto_ge...
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Altera_Forum
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15 years ago

The warning refers to bringing the clock signal to an external pin. It has no relation to the internal registers.