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Altera_Forum's avatar
Altera_Forum
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13 years ago

std_logic_vector type does not match integer literal

Error (10517): VHDL type mismatch error at Transmit2.vhd(118): std_logic_vector type does not match integer literal

at

constant preamble : STD_LOGIC_VECTOR (31 DOWNTO 0) := 16#55#; -- 16 bits * 2 = 32

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    std_logic_vector type does not match integer literal

    --- Quote End ---

    That's true according to VHDL specification. Unless you apply a type conversion, std_logic_vector can be only assigned to a bit string literal of correct bit length, e.g. 

    constant preamble : STD_LOGIC_VECTOR (31 DOWNTO 0) := x"00000055";
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    i got it, so that i write for hex number, in the another post, i thought it as an integer