Altera_ForumHonored Contributor13 years agostd_logic_vector type does not match integer literal Error (10517): VHDL type mismatch error at Transmit2.vhd(118): std_logic_vector type does not match integer literal at constant preamble : STD_LOGIC_VECTOR (31 DOWNTO 0) := 16#55#; -- 16 b...Show More
Altera_ForumHonored Contributor13 years agosuccess For hex number 16## <- this wrong x"" <- this correct
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