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I am trying to write the VHDL code to do the same job as a few of the modules! I used SLV's with these modules and it all worked OK. Then I came back to the code and started using Integers to do the calculation and found I soon went past 32bits and overflowed some of my variables (as i believe integers are limited to 32bit). So I went back and started using SLV's in my claculations as I suspect they cannot be limited in the same way as integers.
But you say that unsigned is the way to go? Can I get past 32bit arithmetic problems this way?
Many thanks again tricky for your quick response!
D
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Technically, integer has no bits, but it's maximum value is determined by the compiler. I think the VHDL LRM allows for any sized integer (8, 16, 32 or 64bit), but everyone sticks with 32 bits (well not quite - range is -2^-31+1 to 2^31-1, so not quite the full 32 bits range). Unisnged and signed are just arrays that allows the user to set the size using a natual, so an unsigned, signed or std_logic_vector can be up to 2^31 bits wide. SO yes, you get well around the integer limitations doing this (But never try to cast a number wider than 32 bits - 31 for unsigned - back to an integer type).
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Pay attention to x"3F" that might be considered as a negative number.
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It wont be in unsigned arithmatic.