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Altera_Forum
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13 years ago

STD_LOGIC_VECTOR multipication

I keep getting an error using the '*' to multiply SLV's: use IEEE.numeric.std.all; constant COEFF : STD_LOGIC_VECTOR (5 downto 0) := x"3F"; signal EXPx63_LTCHD : S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I am trying to write the VHDL code to do the same job as a few of the modules! I used SLV's with these modules and it all worked OK. Then I came back to the code and started using Integers to do the calculation and found I soon went past 32bits and overflowed some of my variables (as i believe integers are limited to 32bit). So I went back and started using SLV's in my claculations as I suspect they cannot be limited in the same way as integers.

But you say that unsigned is the way to go? Can I get past 32bit arithmetic problems this way?

Many thanks again tricky for your quick response!

D