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Altera_Forum
Honored Contributor
7 years agoHi Emil,
--- Quote Start --- can you explain me why I get different state transition diagram from relatively the same VHDL? --- Quote End --- Here VHDL codes aren`t same, It leads the different state transition diagram, 1) rx_bit_index <= 0; In all cases except when rx_bit_index has value ranges from 0 to 6; 2) rx_bit_index <= 0; only when if rx_bit_index = 7 Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards Vikas Jathar Intel Customer Support – Engineering (Under Contract to Intel)