SR latch test bench help

Im having problems getting an output in the simulator in modelsim for rl sl qa and qb, i changed the code a bit so it shows r s and q on the simulator.

library ieee;

use ieee.std_logic_1164.all;

entity Testbench6a is

end Testbench6a;

architecture struct of Testbench6a is

component tut6a

port ( clk , r , s : in std_logic;

q : out std_logic);

end component;

signal s , r , q : std_logic := '0';

signal rl , sl , qa , qb : std_logic := '0';

signal clk : std_logic := '1';

begin

inst1 : tut6a port map( clk ,

r ,

s ,

q );

process

begin

s <= '0';

r <= '0';

wait for 10 ns;

s <= '1';

r <= '0';

wait for 10 ns;

s <= '0';

r <= '1';

wait for 10 ns;

s <= '1';

r <= '1';

wait;

end process;

end architecture;