SR latch test bench help

Hey im not sure how to make a testbench for an sr latch, the code ive made is shown below for the latch and the testbench.

for the latch

library ieee;

use ieee.std_logic_1164.all;

entity tut6a is

port (

end tut6a;

architecture struct of tut6a is

signal r1 , s1, qa , qb : std_logic;

attribute keep : boolean;

attribute keep of r1 , s1 , qa , qb : signal is true;

begin

r1 <= r and clk;

s1 <= s and clk;

qb <= not (r1 and qa);

qa <= (s1 and qb);

q <= qa;

end struct;

for the testbench

library ieee;

use ieee.std_logic_1164.all;

entity Testbench6a is

end Testbench6a;

architecture struct of Testbench6a is

component tut6a

port ( clk , r , s : in std_logic;

qa , qb , rl , sl : out std_logic);

end component;

signal s , r , q : std_logic := '0';

signal rl , sl , qa , qb : std_logic := '0';

signal clk : std_logic := '1';

begin

inst1 : tut6a port map( clk ,

r ,

s ,

qa,

qb,

rl,

sl );

process

begin

s <= '1';

r <= '0';

wait for 10 ns;

s <= '0';

r <= '1';

wait for 10 ns;

s <= '1';

r <= '1';

wait for 10 ns;

end process;

end architecture;