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Altera_Forum's avatar
Altera_Forum
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8 years ago

SR latch test bench help

Hey im not sure how to make a testbench for an sr latch, the code ive made is shown below for the latch and the testbench. for the latch library ieee; use ieee.std_logic_1164.all; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

What exactly do you need help with? It looks like you are following a tutorial (given an entity name name tut6a). If so, did you read something in this tutorial, or the ones before, regarding port mapping and such things?