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Altera_Forum
Honored Contributor
Honored ContributorSPI core as Master mode?
Hi. Still getting the ropes here. I'm including SPI peripherals to my design for Max10 FPGA. Is it possible instantiate an SPI core in Platform Designer as master?, using Max10 FPGA?, Quartus Prime...
Altera_ForumHonored Contributor
Honored ContributorSo to clarify, I see many mentions of SPI Master mode in the docs and vids, but have yet to land on what register to set, or which core variant of those available should be chosen, in order to instantiate a SPI master in Max10 to address and read/write SPI peripherals. It is ambiguous when just getting the ropes.
The Avalon SPI core doc. PDF references both modes, but doesn't show how to set master more, unless my eyes are just not seeing it. Also there is no dialog entry to set 'master' or 'slave' when adding SPI core to Platform Designer. Yet From Altera 'Embedded Peripherals IP User Guide' it suggests I can set the mode myself: 5.2.4. Master and Slave Modes At system generation time, the designer configures the SPI core in either master mode or slave mode. The mode cannot be switched at runtime. But how? Is there a document I haven't found yet? Thanks in advance.
