SOPC Component Editor

Even though you don't need it, you should add a single address bit to your interface. Also, I don't know how wide you made your data bus but you probably ought to make it 32-bits even though you are only using 16. Otherwise, the Avalon bus will execute two reads to your module every time the NIOS does a read.

Try adding the address and see what that does.

Now on top of this, the rules change a little bit when you are doing a tristate slave.

Also, from the Avalon Interface Specifications document:

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5.1.1. address Behavior

For Avalon-MM tristate slaves, the address signal represents a byte

address. The address signal can be shared among multiple off-chip

devices which have differing data widths. If the Avalon-MM tristate slave

port data width is greater than one byte, it is necessary to correctly map

the address signals from the system interconnect fabric to the address

lines on the slave peripheral.

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You should read the document if you haven't already:

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

Jake

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As I only require a single address (the base address) for the read, I removed the address signals from the template - this resulted in a Warning: 's0: Slave has data signal but no address signal'. Does this matter?

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Yes it does matter. The processor identifies the peripherals by address mapping so you need to specify an address line.

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Also, in address map, I note that 1K of address space has been allocated to this component (0x00000000 to 0x000003FF). Why is this?

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Even if there is a single address that you want for your peripheral, there would always be atleast two addresses possible for the peripheral. This is because if you have only one address line, it will always result in two different addresses ('0' and '1' with appropriate prefixes; an enlargement of this space depends on specific processor bus arbitration rules). Since Nios has dedicated component signals, you need to bear with this ambiguity though it really doesn't affect the operation of either Nios or the peripheral.

I tried specifying a single address line (even though section 5.1 (Table 5.1) of the Avalon Spec suggests that it isn't required). The allocated address space is still 1K - is this possibly just a feature of the Avalon bus as Vizziee suggests in his reply?

A standard PIO port seems to allocated 16 address locations regardless of the width specified.

Thanks for the reminder about the address mapping to the peripheral address lines.

Tim

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I tried specifying a single address line (even though section 5.1 (Table 5.1) of the Avalon Spec suggests that it isn't required). The allocated address space is still 1K - is this possibly just a feature of the Avalon bus as Vizziee suggests in his reply?

A standard PIO port seems to allocated 16 address locations regardless of the width specified.

Thanks for the reminder about the address mapping to the peripheral address lines.

Tim

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Yes it is a feature of the Avalon bus. Unlike standard textbook address buses, it doesn't allocate space only by the number of bits allocated. It follows bus arbitration which would give more space to the peripheral.