--- Quote Start ---
I tried specifying a single address line (even though section 5.1 (Table 5.1) of the Avalon Spec suggests that it isn't required). The allocated address space is still 1K - is this possibly just a feature of the Avalon bus as Vizziee suggests in his reply?
A standard PIO port seems to allocated 16 address locations regardless of the width specified.
Thanks for the reminder about the address mapping to the peripheral address lines.
Tim
--- Quote End ---
Yes it is a feature of the Avalon bus. Unlike standard textbook address buses, it doesn't allocate space only by the number of bits allocated. It follows bus arbitration which would give more space to the peripheral.
Honored Contributor
