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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

some problem about LVDS instantiation

I just simply invoke the LVDS core from megawizard in Quatus 9.0:

input [31:0] rx_in;

input rx_inclock;

output [63:0] rx_out;

and I already declared rx_in,rx_inclock as LVDS in pin planner,but the result from the timer analyzer frustrated me:(in clock setup)

actual fmax :restricted to 500MHz

why??It's difficult to understand,because of the latency from rx_out to the register(i set rx_out as virtual pin)?

what's worse,the max f i could get the right result is 300MHz in modelsim AE

HOW SHOULD I IMPLEMENT THE ENTIRE SYSTEM IF I WANNA TO RUN AT A MUCH HIGHER F?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Although you didn't tell the involved FPGA family, you surely should use a higher SERDES factor, if you intend to "TO RUN AT A MUCH HIGHER F". The maximum LVDS signaling frequency of the respective FPGA has to be kept anyway.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    forget to tell that is STRATIXIII,and the serialization factor for the receiver is 2,so no need to use serializer,as you can refer in the handbook,IOE support DDR mode is the actual instantial process :)

    the actual frequency for my system design is 500MHz input,and deserialized to 250MHz data for further use,but :( i can't get the correct result in modelsim if i set input f >300MHz,so there must be something wrong with my

    implementation,therewithal i looked up the clock setup in Timer Analyzer for answer,here is the key imformation what i see:

    actual fmax: Restricted to 500.00 MHz ( period = 2.000 ns )

    INFO: longest resister to register delay is 1.413ns

    Info: 1: + IC(0.000 ns) + CELL(0.380 ns) = 0.380 ns; Loc. = DDIOINCELL_X0_Y43_N3; Fanout = 1; REG Node = 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|altddio_in:rx_deser_2|ddio_in_89b:auto_generated|dataout_h[25]'

    Info: 2: + IC(0.716 ns) + CELL(0.317 ns) = 1.413 ns; Loc. = FF_X1_Y55_N1; Fanout = 1; REG Node = 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[50]'

    so does that mean that the problem is caused by the delay from rx_out to resister is beyond my f constraint?or=>?how can i solve this problem?