Honored Contributor
Honored Contributorforget to tell that is STRATIXIII,and the serialization factor for the receiver is 2,so no need to use serializer,as you can refer in the handbook,IOE support DDR mode is the actual instantial process :)
the actual frequency for my system design is 500MHz input,and deserialized to 250MHz data for further use,but :( i can't get the correct result in modelsim if i set input f >300MHz,so there must be something wrong with my implementation,therewithal i looked up the clock setup in Timer Analyzer for answer,here is the key imformation what i see: actual fmax: Restricted to 500.00 MHz ( period = 2.000 ns ) INFO: longest resister to register delay is 1.413ns Info: 1: + IC(0.000 ns) + CELL(0.380 ns) = 0.380 ns; Loc. = DDIOINCELL_X0_Y43_N3; Fanout = 1; REG Node = 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|altddio_in:rx_deser_2|ddio_in_89b:auto_generated|dataout_h[25]' Info: 2: + IC(0.716 ns) + CELL(0.317 ns) = 1.413 ns; Loc. = FF_X1_Y55_N1; Fanout = 1; REG Node = 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rxreg[50]' so does that mean that the problem is caused by the delay from rx_out to resister is beyond my f constraint?or=>?how can i solve this problem?
