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Altera_Forum
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16 years ago

some problem about LVDS instantiation

I just simply invoke the LVDS core from megawizard in Quatus 9.0: input [31:0] rx_in; input rx_inclock; output [63:0] rx_out; and I already declared rx_in,rx_inclock as LVDS in pin planner,b...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Although you didn't tell the involved FPGA family, you surely should use a higher SERDES factor, if you intend to "TO RUN AT A MUCH HIGHER F". The maximum LVDS signaling frequency of the respective FPGA has to be kept anyway.