Some MegaWizard functions fail to generate under Ubuntu/Linux.

Here is what I get when trying to generate a VHDL LPDDR3 MegaWizard function:

Error: Execution of script /tmp/alt7792_3652598158804097740.dir/0019_pll0_gen/proj.tcl failed
Error: Info: *******************************************************************
Error: Info: Running Quartus Prime Shell
Error: Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Error: Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
Error: Info: Your use of Intel Corporation's design tools, logic functions
Error: Info: and other software and tools, and its AMPP partner logic
Error: Info: functions, and any output files from any of the foregoing
Error: Info: (including device programming or simulation files), and any
Error: Info: associated documentation or information are expressly subject
Error: Info: to the terms and conditions of the Intel Program License
Error: Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Error: Info: the Intel FPGA IP License Agreement, or other applicable license
Error: Info: agreement, including, without limitation, that your use is for
Error: Info: the sole purpose of programming logic devices manufactured by
Error: Info: Intel and sold by Intel or its authorized distributors.  Please
Error: Info: refer to the applicable agreement for further details.
Error: Info: Processing started: Tue Sep 18 12:11:15 2018
Error: Info: Command: quartus_sh -t /tmp/alt7792_3652598158804097740.dir/0019_pll0_gen/proj.tcl
Error: Info (23030): Evaluation of Tcl script /tmp/alt7792_3652598158804097740.dir/0019_pll0_gen/proj.tcl was successful
Error: Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
Error: Info: Peak virtual memory: 776 megabytes
Error: Info: Processing ended: Tue Sep 18 12:11:16 2018
Error: Info: Elapsed time: 00:00:01
Error: Info: Total CPU time (on all processors): 00:00:00
Error: Inconsistency detected by ld.so: dl-close.c: 811: _dl_close: Assertion `map->l_init_called' failed!
Error: Execution of script run_simgen_cmd.tcl failed
Error: Info: *******************************************************************
Error: Info: Running Quartus Prime Shell
Error: Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Error: Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
Error: Info: Your use of Intel Corporation's design tools, logic functions
Error: Info: and other software and tools, and its AMPP partner logic
Error: Info: functions, and any output files from any of the foregoing
Error: Info: (including device programming or simulation files), and any
Error: Info: associated documentation or information are expressly subject
Error: Info: to the terms and conditions of the Intel Program License
Error: Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Error: Info: the Intel FPGA IP License Agreement, or other applicable license
Error: Info: agreement, including, without limitation, that your use is for
Error: Info: the sole purpose of programming logic devices manufactured by
Error: Info: Intel and sold by Intel or its authorized distributors.  Please
Error: Info: refer to the applicable agreement for further details.
Error: Info: Processing started: Tue Sep 18 12:11:16 2018
Error: Info: Command: quartus_sh -t run_simgen_cmd.tcl
Error: Info: *******************************************************************
Error: Info: Running Quartus Prime Analysis & Synthesis
Error: Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
Error: Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
Error: Info: Your use of Intel Corporation's design tools, logic functions
Error: Info: and other software and tools, and its AMPP partner logic
Error: Info: functions, and any output files from any of the foregoing
Error: Info: (including device programming or simulation files), and any
Error: Info: associated documentation or information are expressly subject
Error: Info: to the terms and conditions of the Intel Program License
Error: Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Error: Info: the Intel FPGA IP License Agreement, or other applicable license
Error: Info: agreement, including, without limitation, that your use is for
Error: Info: the sole purpose of programming logic devices manufactured by
Error: Info: Intel and sold by Intel or its authorized distributors.  Please
Error: Info: refer to the applicable agreement for further details.
Error: Info: Processing started: Tue Sep 18 12:11:16 2018
Error: Info: Command: quartus_map lpddr2_vhdl_pll0.qpf --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_parameter=SIMGEN_INITIALIZATION_FILE=/tmp/alt7792_3652598158804097740.dir/0019_pll0_gen/simgen_init.txt,CBX_HDL_LANGUAGE=VHDL --simgen_arbitrary_blackbox=+lpddr2_vhdl_pll0_sim_delay
Error: Info (20034): Auto device selection is not supported for Cyclone V device family. The default device, 5CGXFC7C7F23C8, is set.
Error: Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Error: Info (20030): Parallel compilation is enabled and will use 16 of the 16 processors detected
Error: Info (12021): Found 2 design units, including 1 entities, in source file lpddr2_vhdl_pll0_sim_delay.vhd
Error: Info (12022): Found design unit 1: lpddr2_vhdl_pll0_sim_delay-behavior File: /tmp/alt7792_3652598158804097740.dir/0019_pll0_gen/lpddr2_vhdl_pll0_sim_delay.vhd Line: 27
Error: Info (12023): Found entity 1: lpddr2_vhdl_pll0_sim_delay File: /tmp/alt7792_3652598158804097740.dir/0019_pll0_gen/lpddr2_vhdl_pll0_sim_delay.vhd Line: 18
Error: Info (12021): Found 1 design units, including 1 entities, in source file lpddr2_vhdl_pll0.sv
Error: Info (12023): Found entity 1: lpddr2_vhdl_pll0 File: /tmp/alt7792_3652598158804097740.dir/0019_pll0_gen/lpddr2_vhdl_pll0.sv Line: 23
Error: Info (12102): Following modifications are made to the Simgen blackbox list
Error: Info (12105): "lpddr2_vhdl_pll0_sim_delay" inserted to the Simgen black box list
Error: Info (12127): Elaborating entity "lpddr2_vhdl_pll0" for the top level hierarchy
Error: Info (10648): Verilog HDL Display System Task info at lpddr2_vhdl_pll0.sv(157): Using Fast pll emif simulation models File: /tmp/alt7792_3652598158804097740.dir/0019_pll0_gen/lpddr2_vhdl_pll0.sv Line: 157
Error: Info (281010): Generating sgate simulator netlist using Simgen
Error: SIMGEN_PROGRESS Start of Model generation -- 0% complete
Error: SIMGEN_PROGRESS Phase 1 : Internal Objects created -- 25% complete
Error: SIMGEN_PROGRESS Phase 2 : Connections between internal objects made -- 60% complete
Error: SIMGEN_PROGRESS Phase 3 : Netlist generated -- 100% complete
Error: Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Error: Info: Peak virtual memory: 1011 megabytes
Error: Info: Processing ended: Tue Sep 18 12:11:25 2018
Error: Info: Elapsed time: 00:00:09
Error: Info: Total CPU time (on all processors): 00:00:25
Error: Inconsistency detected by ld.so: dl-close.c: 811: _dl_close: Assertion `map->l_init_called' failed!
Error: Info (23030): Evaluation of Tcl script run_simgen_cmd.tcl was successful
Error: Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
Error: Info: Peak virtual memory: 763 megabytes
Error: Info: Processing ended: Tue Sep 18 12:11:25 2018
Error: Info: Elapsed time: 00:00:09
Error: Info: Total CPU time (on all processors): 00:00:26
Error: Inconsistency detected by ld.so: dl-close.c: 811: _dl_close: Assertion `map->l_init_called' failed!
<html>Info: "<b>lpddr2_vhdl</b>" instantiated <b>altera_mem_if_lpddr2_pll</b> "<b>pll0</b>"
Error: Generation stopped, 7 or more modules remaining

Since my post size is limited, I only included the error messages.