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Altera_Forum's avatar
Altera_Forum
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14 years ago

Some bits in reg are disappeared!

I wrote a project at Quartus II 9.1.But the resulst is always wrong.I fond some bits in some registers are disappeared!For instance the are only 6 bits in reg [7:0] max_value, 2 bits are disappeared! But if I set this "max_value" as an output and connect it to a outpin all 8 bits are there and the result is right.I think maybe the problem could be done by some settings in Quartus II. But I don't find. Could any body please help me?

Thanks!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Try a clear question. Where are you missing the register bits? In a simulation, in Signal Tap output?

    The most likely explanation is, that the bits are not used in the design and have been discarded, or the signals are not present at the place, where you try to tap them.

    P.S.: Please avoid cross postings.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Try a clear question. Where are you missing the register bits? In a simulation, in Signal Tap output?

    The most likely explanation is, that the bits are not used in the design and have been discarded, or the signals are not present at the place, where you try to tap them.

    P.S.: Please avoid cross postings.

    --- Quote End ---

    I'm sorry for cross postings.

    The error appears in Signal Tap output.

    Because the result of the project is not right,I add some items to Signal Tap to find the place where the error occurs.I found the missing register bits. But when I connect it to a output pin,in fact I don't want this output pin,no missing register bits occurs again. And the result of the whole project is right also.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    As I already it's most likely not an error. SignalTap's representation is hardware related. If you display a bit-vector register, but some bits aren't actually existing as register bits, they aren't recorded and not filled in when displaying the values.

    Your observation, that the design output changes, when the "missing bits" are exposed as outputs, needs further explanation. If these bits are unequivocally processed for the final design output, they won't be discarded. There must be something special with your design.