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Altera_Forum's avatar
Altera_Forum
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12 years ago

single_port_rom .hex initialisation file

Hi,

I added a single port rom entity to my VHDL via "Edit" --> "Insert Template". I specified the initialisation file as "rom.hex", but it is initialising using a MIF file. The MIF filename has been generated by the system.

How do I force it to use my .hex file?

Thanks,

Mark

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Tried again, this time using the Wizard. Accepts the .hex file name and that part is fine.

    Unfortuntely, the VHDL created by the Wizard for altsyncram uses type std_logic_vector for the address, whereas the template version uses the (far nice) natural type. Shame :(

    So, working, but the VHDL now has lots of things like 

    
tmpIP := tmpIP + 1; -- tmpIP is a natural
IP <= std_LOGIC_VECTOR(to_unsigned(tmpIP, IP'length)); -- IP is a std_logic_vector, as per the altsyncram "address"
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You can always write a wrapper component around the Megawizard generated code, just to use a natural for the address. It won't add any logic to the design, so you will have no timing or space penalty, but it can make the code nicer.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    You can always write a wrapper component around the Megawizard generated code, just to use a natural for the address. It won't add any logic to the design, so you will have no timing or space penalty, but it can make the code nicer.

    --- Quote End ---

    Darn it, why didn't I think of that :oops:

    Thank you for helping.