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Altera_Forum
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13 years ago

single_port_rom .hex initialisation file

Hi, I added a single port rom entity to my VHDL via "Edit" --> "Insert Template". I specified the initialisation file as "rom.hex", but it is initialising using a MIF file. The MIF filename has...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Tried again, this time using the Wizard. Accepts the .hex file name and that part is fine.

Unfortuntely, the VHDL created by the Wizard for altsyncram uses type std_logic_vector for the address, whereas the template version uses the (far nice) natural type. Shame :(

So, working, but the VHDL now has lots of things like 


tmpIP := tmpIP + 1; -- tmpIP is a natural
IP <= std_LOGIC_VECTOR(to_unsigned(tmpIP, IP'length)); -- IP is a std_logic_vector, as per the altsyncram "address"