Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Simulation problem: altera_pll - The design unit was not found

Hello

I create a simple project to practice Quartus II (v13.0.1)

A simple design include a PLL that generated by MegaWizard

when I simulate my design using ModelSim ALTERA STARTER EDITION 10.1d

I got an error message--------------

# Loading work.rt0_top# Loading work.ip0_pll# ** Error: (vsim-3033) D:/jamieliao/Try_QuartusII/Megafunction/ip0_pll_sim/ip0_pll.vo(51): Instantiation of 'altera_pll' failed. The design unit was not found.# # Region: /rt0_top/IP_0# Searched libraries:# D:/jamieliao/Try_QuartusII/Project/simulation/rtl_work# Loading work.rt1_pll_rst_flow# Error loading design

I found altera_pll.v file at ...\13.0sp1\quartus\libraries\megafunctions\altera_pll.v

I was wondering to know how to link the libary file to simulator.

Is there a properties setting that can let all the magafunctions link to simulator automatically.

thank you

Jamie

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    why don't you remove the pll instance just for the simulation ?

    Otherwise, I think you should update and compile altera libraries under modelsim.

    (but i'm not sure that one can simulate a pll..)

    regards,

    PS : may be a particular device pll could be simulated (ex : cyclone_pll).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hello,

    I was also facing same problem and I could solve it by adding "altera_lnsim_ver" library. ( This library is for verilog. And same can be found for VHDL. ) I was simulating Stratix V device in Quartus 13.1.

    Hope this would be helpful to someone.

    Cheers,

    Bhaumik
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Hello,

    I was also facing same problem and I could solve it by adding "altera_lnsim_ver" library. ( This library is for verilog. And same can be found for VHDL. ) I was simulating Stratix V device in Quartus 13.1.

    Hope this would be helpful to someone.

    Cheers,

    Bhaumik

    --- Quote End ---

    Exactly!

    But I could not adding altera_mf_ver( included alt_pll also). Have you any solution for this problem?

    Regard,

    ToanRV.